The present invention relates to a method of manufacturing a semiconductor device, and more specifically to a method of manufacturing a semiconductor device wherein the testing process of the semiconductor device is simplified and made efficient.
In the process of manufacturing semiconductor devices, especially for a testing apparatus used in the testing process, JP-A-7-7052 discloses a testing apparatus using probes for measuring electrical properties fabricated by forming a metal film for conduction on a surface of cantilever structures consisting of single crystal silicon, and holding these by an insulating substrate whereon a conductive wiring pattern is formed. JP-A-2001-56344 discloses a testing apparatus, in which film state probe units forming plural wires on sheet state materials have a plurality of rectangular probe regions in a matrix state, and each of the probe units is fixed on a single substrate. JP-A-2001-7165 discloses a testing apparatus comprising an insulator board, and a probe card wafer consisting of the same material as the wafer to be measured and having a plurality of bumps disposed thereon, and the probe card wafer has a spacer for sealing between the wafer to be measured and the probe card wafer, and a wafer through-hole for vacuum suction in order to vacuum suctioning the wafer to be measured.
However, by the constitution disclosed in JP-A-7-7052, if the number of probes is to be increased, it becomes difficult to secure the region for forming each wiring. This is because the wiring must run from the probes (protrusions) of the cantilever, pass on the plane (surface) whereon the probes are formed, and reach secondary electrodes formed on an circumferential side of the substrate (e.g., single crystal silicon) that forms the probes, and must detour other wiring or elements present in the course.
Although the constitution wherein a large number of probes are disposed is disclosed in JP-A-2001-56344 or JP-A-2001-7165, no structures intending good contact or conduction as a whole even if there are warps and the like in the substrate and the wafer are disclosed; and no specific methods for supporting and fixing each probe unit to the substrate are also disclosed.
For example, if positional accuracy is thus relatively insufficient between probe units, troubles that the probes cannot come into contact with the pads of the wafer to be tested may be caused. Also in the structure wherein each probe unit is always substantially fixed to a single substrate, the manufacturing costs of the substrate for constituting the entire structure may become enormous. In addition, for example, if malfunction occurs in one wiring in the wiring system from the probes to the external system, all of wiring must be replaced for the nature of the testing apparatus, and enormous costs are required for the repair thereof. Furthermore, when a wide area in the wafer of a large area (diameter) is to be covered, the warps of the substrate and the wafer cannot be absorbed, and defects in function, that uniform contact cannot be performed at specific places, may occur.
An object of the present invention is to solve such problems, and to provide a method of manufacturing a semiconductor device that can manufacture the semiconductor device easily and efficiently by disposing a sufficient number of probes to cover a whole wide area, such as the entire area of a wafer to be tested, and carrying out a semiconductor testing process that can bring the probes into good contact with the wafer to be tested.